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FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Integrated Device Technology, Inc.
IDT54/74FCT16501AT/CT/ET IDT54/74FCT162501AT/CT/ET IDT54/74FCT162H501AT/CT/ET
CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type * Common features: flip-flops to allow data flow in transparent, latched and clocked - 0.5 MICRON CMOS Technology modes. Data flow in each direction is controlled by output- High-speed, low-power CMOS replacement for enable (OEAB and OEBA), latch enable (LEAB and LEBA) ABT functions and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, - Typical tSK(o) (Output Skew) < 250ps the device operates in transparent mode when LEAB is HIGH. - Low input and output leakage 1A (max.) When LEAB is LOW, the A data is latched if CLKAB is held at - ESD > 2000V per MIL-STD-883, Method 3015; a HIGH or LOW logic level. If LEAB is LOW, the A bus data > 200V using machine model (C = 200pF, R = 0) is stored in the latch/flip-flop on the LOW-to-HIGH transition of - Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack CLKAB. OEAB is the output enable for the B port. Data flow from the B port to the A port is similar but requires using OEBA, - Extended commercial range of -40C to +85C LEBA and CLKBA. Flow-through organization of signal pins * Features for FCT16501AT/CT/ET: simplifies layout. All inputs are designed with hysteresis for - High drive outputs (-32mA IOH, 64mA IOL) improved noise margin. - Power off disable outputs permit "live insertion" The FCT16501AT/CT/ET are ideally suited for driving - Typical VOLP (Output Ground Bounce) < 1.0V at high-capacitance loads and low-impedance backplanes. The VCC = 5V, TA = 25C output buffers are designed with power off disable capability * Features for FCT162501AT/CT/ET: to allow "live insertion" of boards when used as backplane - Balanced Output Drivers: 24mA (commercial), drivers. 16mA (military) The FCT162501AT/CT/ET have balanced output drive - Reduced system switching noise with current limiting resistors. This offers low ground bounce, - Typical VOLP (Output Ground Bounce) < 0.6V at minimal undershoot, and controlled output fall times-reducing VCC = 5V,TA = 25C the need for external series terminating resistors. The * Features for FCT162H501AT/CT/ET: FCT162501AT/CT/ET are plug-in replacements for the - Bus Hold retains last active bus state during 3-state FCT16501AT/CT/ET and ABT16501 for on-board bus inter- Eliminates the need for external pull up resistors face applications. The FCT162H501AT/CT/ET have "Bus Hold" which reDESCRIPTION: tains the input's last state whenever the input goes to high The FCT16501AT/CT/ET and FCT162501AT/CT/ET 18- impedance. This prevents "floating" inputs and eliminates the bit registered transceivers are built using advanced dual metal need for pull-up/down resistors.
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKBA LEBA OEBA CLKAB LEAB C A1 D C B1 D
C D
C D
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-2547/8
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND
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OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
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GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND
SSOP/ TSSOP/TVSOP TOP VIEW
CERPACK TOP VIEW
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names OEAB Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs
(1) (1)
FUNCTION TABLE(1,4)
Inputs LEAB CLKAB X H H L L L L X X X L H Outputs Bx Z L H L H B(2) B(3)
OEBA
LEAB LEBA CLKAB CLKBA Ax Bx
OEAB L H H H H H H
Ax X L H L H X X
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTE: 2547 tbl 01 1. On FCT16xH501T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to -0.5 to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Unit V V C mA
NOTES: 2547 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = LOW-to-HIGH Transition
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
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CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF
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NOTE: 1. This parameter is measured at characterization but not tested.
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (STANDARD PARTS)
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input pins)(5) VCC = Max. VCC = Min., IIN = -18mA VCC = Max., VO = GND (3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = GND VO = 2.7V VO = 0.5V
Min. 2.0 -- -- -- -- -- -- -- -- -80 -- --
Typ.(2) --
-- -- -- -- -- -- -- -0.7 -140
Max.
--
Unit V V A
0.8 1 1 1 1 1 1
-1.2 -225 --
Input LOW Current (I/O pins)(5) High Impedance Output Current (3-State Output pins) (5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current
A V mA mV A
100 5
VCC = Max., VIN = GND or VCC
500
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OUTPUT DRIVE CHARACTERISTICS FOR FCT16501T
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage Test Conditions(1) VCC = Max., VO = 2.5V(3) VCC = Min. VIN = VIH or VIL IOH = -3mA IOH = -12mA MIL. IOH = -15mA COM'L. IOH = -24mA MIL. IOH = -32mA COM'L.(4) VCC = Min. IOL = 48mA MIL. VIN = VIH or VIL IOL = 64mA COM'L. VCC = 0V, VIN or VO 4.5V Min. -50 2.5 2.4 2.0 -- -- Typ.(2)
--
Max.
-180
Unit mA V V V V A
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3.5 3.5 3.0 0.2 --
-- -- -- 0.55 1
VOL IOFF
Output LOW Voltage Input/Output Power Off Leakage(5)
OUTPUT DRIVE CHARACTERISTICS FOR FCT162501T
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL. IOH = -24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V
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NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) II L Input LOW Current(4) IBHH IBHL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Bus Hold Standard Standard Input(5) I/O(5) Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2.0 -- -- -- -- -- VI = GND -- -- -- -- VCC = Min. VI = 2.0V VI = 0.8V VCC = Max. VCC = Min., IIN = -18mA VCC = Max., VO = GND(3)
--
Typ.(2) -- -- -- -- -- -- -- -- -- -- -- --
-- -- -0.7 -140
Max.
--
Unit V V
0.8
1 1 100 100 1 1 100 100
-- --
A
Bus-Hold Input Bus-Hold I/O Standard Input(5) Standard I/O(5) Bus-Hold Input Bus-Hold I/O Bus-Hold Input
-50 +50 -- -- -- -80 -- --
A
Sustain Current(4) High Impedance Output Current (3-State Output pins) (5,6) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current
VO = 2.7V VO = 0.5V
1 1
-1.2 -225 --
A
V mA mV
100 5
VCC = Max., VIN = GND or VCC
500
A
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Pins with Bus Hold are identified in the pin description. 5. The test limit for this parameter is 5A at TA = -55C. 6. Does not include Bus Hold I/O pins.
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max., Outputs Open VIN = VCC OEAB = OEBA = VCC or GND VIN = GND One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND Min. -- -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA A/ MHz
IC
Total Power Supply Current(6)
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
3.8
6.5(5)
VIN = 3.4V VIN = GND
--
8.5
20.8(5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16501AT/162501AT Com'l. Symbol Parameter Condition(1) Min.(2) Max. Mil. Min.(2) Max. FCT16501CT/162501CT Com'l. Min.(2) Max. Mil. Min.(2) Max. FCT16501ET/162501ET Com'l. Min.(2) Max. Mil. Min.(2) Max. Unit
fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU
CLKAB or CLKBA frequency(4)
CL = 50pF RL = 500
-- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 --
150 5.1 5.6 5.6 6.0 5.6 -- -- -- -- -- -- -- 0.5
-- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 --
150 5.6 6.0 6.0 6.4 6.0 -- -- -- -- -- -- -- 0.5
-- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 --
150 4.6 5.3 5.3 5.6 5.2 -- -- -- -- -- -- -- 0.5
-- 1.5 1.5 1.5 1.5 1.5 3.0 0 3.0 1.5 1.5 3.0 3.0 --
150 4.6 5.6 5.4 6.0 5.6 -- -- -- -- -- -- -- 0.5
-- 1.5 1.5 1.5 1.5 1.5 2.4 0 2.0 1.5 0.5 3.0 3.0 --
150 3.8 4.2 4.2 4.8 5.2 -- -- -- -- -- -- -- 0.5
-- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA tH Hold Time HIGH or LOW Ax to CLKAB, Bx to CLKBA tSU Set-up Time Clock HIGH or LOW LOW Ax to LEAB, Clock Bx to LEBA HIGH tH Hold Time, HIGH or LOW Ax to LEAB, Bx to LEBA tW LEAB or LEBA Pulse Width HIGH(4) tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) tSK(o) Output Skew (3)
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested.
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
2547 lnk 11 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Switch
Closed
2547 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
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LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
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tSU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
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ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
2547 drw 08
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ
VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT X FCT X Temperature Drive Range X XXXX X Bus Hold Device Type Package X Process
Blank B PV PA PF E 501AT 501CT 501ET Blank H 16 162 54 74
Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) Non-Inverting 18-Bit Registered Transceiver
Standard Bus Hold 16-Bit High Drive 16-Bit Balanced Drive -55C to +125C -40C to +85C
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